Integrated Circuit (IC) technology has developed to a point where a large number of complete circuits can be manufactured on the same semiconductor wafer using planar technology. The circuits are typically incorporated onto the wafer using photolithographic techniques. Each circuit can contain a large number of components such as transistors, diodes, resistors, capacitors, etc., which are electrically interconnected in preselected arrangements. After the circuit components are formed on the wafer, the wafer is tested and diced into individual chips comprising selected arrays of circuits, which are further processed and encapsulated into common bipolar or FET ICs.
Photolithographic technology is widely used for forming the circuit patterns on the semiconductor wafers where good resolution and high yield are required. Using optical stepping techniques, the patterns initially formed on an optical mask substrate can be transferred optically onto a photoresist layer of a wafer by a step and repeat method. The step and repeat method comprises moving the mask, which contains the pattern for a portion of the wafer, to an unexposed section of the wafer and using electromagnetic radiation to image the mask pattern onto the wafer. After the pattern is imaged, the wafer is moved and the exposure is repeated. The step and repeat method for each photolithographic step continues until the entire wafer has been exposed.
The original photolithographic techniques used ultraviolet or natural light to expose the patterns on the wafer. However, ultraviolet and natural light techniques have resolution limitations. In particular, diffraction, interference, and/or light divergence is common, which causes a reduction in resolution and limits the circuit yield per wafer. In the case of very complex integrated circuits (e.g. VLSI), the size of the components forming the circuits approaches the wave lengths used to produce the masks (around 1 .mu.m) and large geometric errors can thereby arise. The resolution ultimately obtained in the resist is thus limited by, among other factors, the wavelength of the incident light.
In part because of these disadvantages, X-ray lithography was developed to take advantage of the shorter wavelengths of the soft X-rays to expose appropriate patterns in the resists. The wavelength of the X-rays generally range from about 0.1 to 1.0 nanometers, which significantly improves the resolution and circuit yield per wafer associated with lithography.
During X-ray lithography, an X-ray source such as a synchrotron is used to direct an intense collimated beam of X-rays through an X-ray mask overlying a photoresist layer of a semiconductor wafer. The mask includes a central, X-ray transparent region with selected patterns formed of X-ray absorbing material.
The X-rays expose patterns on the underlying photoresist layer that correspond to the apertures in the mask formed by the X-ray absorbing material. However, because of the short wavelength of the X-rays, the diffraction, interference and/or divergence of the X-rays is minimized. Moreover, the back-scattering and reflection from the wafer is also reduced. Accordingly, X-ray lithography offers the advantages of improved resolution combined with a large depth of field, vertical walled patterns, and simplicity in forming the circuit patterns on the semiconductor wafers.
To form the X-ray mask substrate for use in X-ray lithography, a flat wafer formed from X-ray opaque material, e.g., silicon, has a square central region on the bottom surface of the wafer etched to a thin tensile membrane using conventional etching techniques, e.g. diffusing an appropriate dopant into the wafer as an etch-stop. The wafer is bonded to a support ring to provide support and stability for the mask. An X-ray absorbing material, e.g., gold, is then selectively deposited on the upper surface of the wafer in the central region in an appropriate circuit pattern by techniques such as electroplating. The finished mask substrate is brought proximate to a positive-acting or negative-acting resist-covered semiconductor wafer, and X-rays are applied to expose corresponding resist patterns on the underlying semiconductor wafer.
Although the X-ray mask substrate improves the resolution capabilities of X-ray lithography, the substrate fabrication process is not without drawbacks. For example, during the fabrication of the mask substrate, the substrate can experience warpage during the membrane etching process which is unacceptable for high definition imaging techniques. The mask must have an extremely flat surface for accurate reproduction of the circuit pattern. The warpage also endangers the mask at the X-ray stepper since the proximity of the mask to the semiconductor wafer is on the order of 40 .mu.m or less.
Moreover, deformation of the X-ray absorbing material in the X and Y directions can occur during the deposition of the X-ray absorbing material on the upper surface of the substrate. One method for controlling this type of deformation is shown in Nakagawa, U.S. Pat. No. 4,881,257. In the Nakagawa patent, deformation is controlled by selectively depositing an X-ray absorbing material, e.g., tungsten or tantalum, on the upper surface of the mask substrate in both the central region and in the area surrounding the central region. The material is deposited such that an equalization of pattern densities is achieved across the substrate. The method disclosed in the Nakagawa patent is particularly suited for reducing the displacement of the X-ray absorbing material in the X and Y directions, but is not directed towards reducing the warpage of the mask substrate itself.
Moreover, it has been observed that most mask warpage is induced during the mask substrate formation steps prior to the bonding step and the deposition of the X-ray absorber material. Accordingly, it has been determined that the greatest opportunity for warpage reduction is available before this bonding step and X-ray absorber material deposition.